1. Field of the Invention
The present invention relates to protective device and, more particularly, to a protective device in which protective elements formed of bipolar transistors are provided at every protected portion so as to prevent breakdown such as a potential shift or the like from being caused at the active portions of a CCD (charge coupled device) solid state imaging device or the like.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a cross section from a horizontal register to an output section of a solid state imaging device of a CCD vertical type overflow drain structure.
Referring to FIG. 1, a channel region 10 of a horizontal CCD 19 is formed on the surface side of a p-type well 16. On the p-type well 16 are formed transfer electrodes which comprise storage gates 11 and transfer gates 12, the gates 11 and 12 each being made of a first polysilicon 1POLY and a second polysilicon 2POLY, respectively. The gates 11 and 12 are insulated from the silicon substrate 16 by means of a gate insulation film 17. Beneath the electrodes of the transfer gates 12 to which horizontal transfer clock signals .phi..sub.H1 and .phi..sub.H2 are applied are ion implantation regions (P.sup.-) 18. The regions 18 are intended to make the potential shallower for implantation of two-phase drive.
A horizontal output gate 9 at the left-hand end of the horizontal CCD 19 is generally kept to a DC potential level such as ground level. A reset gate 13 is provided to reset the change in the potential of an FD (floating diffusion) region 7, the change being attributable to the charge signal given per picture element. With this arrangement, the potential of the FD region 7 is reset to the potential of a reset drain 14.
FIG. 2 is a fragmentary circuit diagram showing the portion of a protective device in which a plurality of portions of a CCD vertical type overflow drain structure solid state imaging device are protected by a plurality of protective elements.
In FIG. 2, reference numerals T1, T2, T3 denote terminals (input terminals), respectively. Reference symbol Lc1 denotes one capacitance load (e.g., gate of transfer register or the like), Lj a junction load (e.g., reset drain of horizontal register), and Lc2 another capacitance load (gate load). Operation voltages A1 to A3 thereof, maximum values a1, a2, a3 of the operation voltages A1 to A3 and breakdown voltages (withstand voltages) D1 to D3 thereof are different as shown in FIG. 3.
As shown in FIG. 2, there are provided bipolar protective transistors Q1.sub.1, Q1.sub.2 and Q1.sub.3 which protect the aforesaid load portions. Collector electrodes C of the respective protective transistors Q1.sub.1, Q1.sub.2 and Q1.sub.3 are formed of an n-type substrate of a CCD solid state imaging device of a vertical type overflow drain structure and are kept at ground level. Base electrodes B thereof are formed of a p-type well region formed on the n-type substrate and to which there is applied a potential of -9 V, for example. Emitter electrodes E of the protective transistors Q1.sub.1, Q1.sub.2 and Q1.sub.3 are connected to terminals on the opposite side of the ground of the loads that are to be protected. In the prior art, characteristics of the protective transistors Q1.sub.1, Q1.sub.2, Q1.sub.3 are exactly the same and the breakdown voltages B thereof also are exactly the same as shown in FIG. 3.
The protecting operation done by the protective transistors will be described below.
When the terminal T is set to low potential, a forward voltage is supplied to an emitter-base path of the protective transistor and the protective transistor is turned on. Thus, a collector current is flowed to the protective transistor and the potential at the terminal T can be prevented from being lowered more than this by the collector current. Therefore, it is possible to prevent the load from being destroyed when the potential at the terminal T is lowered abnormally.
When the potential at the terminal T is increased abnormally, a reverse voltage that is in excess of the breakdown voltage of the protective transistor is applied to the emitter-base path of the protective transistor. Then, an emitter-base junction breaks down so that a current is flowed from the terminal side through the emitter-base path. By this current, it is possible to prevent the potential at the terminal T from being increased in excess of the breakdown voltage. Therefore, the loads can be prevented from being broken by the extraordinary high voltage.
In the prior art, the loads are protected by the same protective transistors Q1.sub.1 to Q1.sub.2 of breakdown voltage B regardless of difference between the withstand voltages and the operation voltages of the protected loads.
Consequently, the loads cannot be protected in an optimum fashion in response to the withstand voltages and the operation voltages thereof. By way of example, breakdown margins E1, E2 are not satisfactory as in the cases 1 and 2 of FIG. 3. If the breakdown voltages B of the protective transistors Q1.sub.1, Q1.sub.2 and Q1.sub.3 are lowered uniformly, then in the case 3 of FIG. 3, the breakdown voltage B approaches the maximum value a3 of the operation voltage to obstruct a stable operation.
In particular, the breakdown voltages B of the protective transistors fluctuate by an amount C upon production. If such fluctuated amount C is taken into consideration, then the breakdown margin becomes smaller. Consequently, the loads cannot be protected reliably and the operation of the protective transistor cannot be stabilized. There is then the problem that cannot be neglected when the loads are protected by the protective transistors of the same breakdown voltage B regardless of the difference of the withstand voltages and the operation voltages.